Simulators

KyuPy’s simulators are optimized for cells with at most 4 inputs and 1 output.

More complex cells must be mapped to simulation primitives first.

Logic Simulation - `kyupy.logic_sim`

A high-throughput combinational logic simulator.

The class LogicSim performs parallel simulations of the combinational part of a circuit. The logic operations are performed bit-parallel on packed numpy arrays (see bit-parallel (bp) array description in logic). Simple sequential circuits can be simulated by repeated assignments and propagations. However, this simulator ignores the clock network and simply assumes that all state-elements are clocked all the time.

class kyupy.logic_sim.LogicSim(circuit: Circuit, sims: int = 8, m: int = 8, c_reuse: bool = False, strip_forks: bool = False)

A bit-parallel naïve combinational simulator for 2-, 4-, or 8-valued logic.

Parameters:

circuit – The circuit to simulate.
sims – The number of parallel logic simulations to perform.
m – The arity of the logic, must be 2, 4, or 8.
c_reuse – If True, intermediate signal values may get overwritten when not needed anymore to save memory.
strip_forks – If True, forks are not included in the simulation model to save memory and simulation time.

s

Logic values of the sequential elements (flip-flops) and ports.

It is a pair of arrays in bit-parallel (bp) storage format:

s[0] Assigned values. Simulator will read (P)PI value from here.
s[1] Result values. Simulator will write (P)PO values here.

Access this array to assign new values to the (P)PIs or read values from the (P)POs.

s_to_c(): Copies the values from s[0] the inputs of the combinational portion.

c_prop(sims=None, inject_cb=None, fault_line: Line | int = -1, fault_mask=None, fault_model=2)

Propagate the input values through the combinational circuit towards the outputs.

Performs all logic operations in topological order. If the circuit is sequential (it contains flip-flops), one call simulates one clock cycle.

Parameters:: inject_cb (f(Line, ndarray)) – A callback function for manipulating intermediate signal values. This function is called with a line and its new logic values (in bit-parallel format) after evaluation of a node. The callback may manipulate the given values in-place, the simulation resumes with the manipulated values after the callback returns. Specifying this callback may reduce performance as it disables jit compilation.

c_to_s(): Copies (captures) the results of the combinational portion to s[1].

s_ppo_to_ppi()

Constructs a new assignment based on the current data in s.

Use this function for simulating consecutive clock cycles.

For 2-valued or 4-valued simulations, all valued from PPOs (in s[1]) and copied to the PPIs (in s[0]). For 8-valued simulations, PPI transitions are constructed from the final values of the assignment (in s[0]) and the final values of the results (in s[1]).

cycle(cycles: int = 1, inject_cb=None)

Repeatedly assigns a state, propagates it, captures the new state, and transfers PPOs to PPIs.

Parameters:

cycles – The number of cycles to simulate.
inject_cb – A callback function for manipulating intermediate signal values. See c_prop().

class kyupy.logic_sim.LogicSim2V(circuit: Circuit, sims: int = 8, c_reuse: bool = False, strip_forks: bool = False)

A bit-parallel naïve combinational simulator for 2-valued logic.

Parameters:

circuit – The circuit to simulate.
sims – The number of parallel logic simulations to perform.
c_reuse – If True, intermediate signal values may get overwritten when not needed anymore to save memory.
strip_forks – If True, forks are not included in the simulation model to save memory and simulation time. Caveat: faults on fanout branches will not be injected if forks are stripped.

c

Logic values within the combinational portion of the circuit.

In bit-parallel (bp) storage format. Storage locations are indirectly addressed. Data for line l is in self.c[self.c_locs[l]].

s_assign

Logic values assigned to the ports and flip-flops of the circuit.

The simulator reads (P)PI values from here. Values assigned to PO positions are ignored. This field is a 2-dimensional array and expects values in the mv storage format. First index is the port position (defined by self.circuit.s_nodes), second index is the pattern index (0 … self.sims-1).

s_result

Logic values at the ports and flip-flops of the circuit after simulation.

The simulator writes (P)PO values here. Values assigned to PI positions are ignored. This field is a 2-dimensional array and expects values in the mv storage format. First index is the port position (defined by self.circuit.s_nodes), second index is the pattern index (0 … self.sims-1).

s_to_c(): Assigns the values from self.s_assign to the inputs of the combinational portion.

c_to_s(): Captures the results of the combinational portion into self.s_result.

c_ppo_to_ppi(): Copies the result data for all PPOs (flip-flops) to PPIs for a next simulation cycle.

allocate(): Allocates a new pattern array with appropriate dimensions (self.s_len, self.sims) for one-pass simulation.

class kyupy.logic_sim.LogicSim4V(circuit: Circuit, sims: int = 8, c_reuse: bool = False, strip_forks: bool = False)

A bit-parallel naïve combinational simulator for 4-valued logic.

Logic values: 0, 1, -, X

Parameters:

circuit – The circuit to simulate.
sims – The number of parallel logic simulations to perform.
c_reuse – If True, intermediate signal values may get overwritten when not needed anymore to save memory.
strip_forks – If True, forks are not included in the simulation model to save memory and simulation time.

c

Logic values within the combinational portion of the circuit.

In bit-parallel (bp) storage format. Storage locations are indirectly addressed. Data for line l is in self.c[self.c_locs[l]].

s_assign: Logic values assigned to the ports and flip-flops of the circuit. The simulator reads (P)PI values from here. Values assigned to PO positions are ignored. This field is a 2-dimensional array and expects values in the mv storage format. First index is the port position (defined by self.circuit.s_nodes), second index is the pattern index (0 … self.sims-1).

s_result: Logic values at the ports and flip-flops of the circuit after simulation. The simulator writes (P)PO values here. Values assigned to PI positions are ignored. This field is a 2-dimensional array and expects values in the mv storage format. First index is the port position (defined by self.circuit.s_nodes), second index is the pattern index (0 … self.sims-1).

s_to_c(): Assigns the values from self.s_assign to the inputs of the combinational portion.

c_to_s(): Captures the results of the combinational portion into self.s_result.

c_ppo_to_ppi(): Copies the result data for all PPOs (flip-flops) to PPIs for a next simulation cycle.

allocate(): Allocates a new pattern array with appropriate dimensions (self.s_len, self.sims) for one-pass simulation.

class kyupy.logic_sim.LogicSim6V(circuit: Circuit, sims: int = 8, c_reuse: bool = False, strip_forks: bool = False)

A bit-parallel naïve combinational simulator for 6-valued logic.

Logic values: 0, 1, R, F, N, P

Parameters:

circuit – The circuit to simulate.
sims – The number of parallel logic simulations to perform.
c_reuse – If True, intermediate signal values may get overwritten when not needed anymore to save memory.
strip_forks – If True, forks are not included in the simulation model to save memory and simulation time.

s

Logic values of the sequential elements (flip-flops) and ports.

It is a pair of arrays in mv storage format:

s[0] Assigned values. Simulator will read (P)PI value from here.
s[1] Result values. Simulator will write (P)PO values here.

Access this array to assign new values to the (P)PIs or read values from the (P)POs.

s_to_c(): Assigns the values from s[0] to the inputs of the combinational portion.

c_to_s(): Captures the results of the combinational portion into s[1].

c_ppo_to_ppi(): Copies the result data for all PPOs (flip-flops) to PPIs for a next simulation cycle.

allocate(): Allocates a new pattern array with appropriate dimensions (self.s_len, self.sims) for one-pass simulation.

Timing Simulation - `kyupy.wave_sim`

High-throughput combinational logic timing simulators.

These simulators work similarly to LogicSim. They propagate values through the combinational circuit from (pseudo) primary inputs to (pseudo) primary outputs. Instead of propagating logic values, these simulators propagate signal histories (waveforms). They are designed to run many simulations in parallel and while their latencies are quite high, they can achieve high throughput.

The simulators are not event-based and are not capable of simulating sequential circuits directly.

Two simulators are available: WaveSim runs on the CPU, and the derived class WaveSimCuda runs on the GPU.

kyupy.wave_sim.TMAX = np.float32(1.7014118e+38): A large 32-bit floating point value used to mark the end of a waveform.

kyupy.wave_sim.TMAX_OVL = np.float32(1.871553e+38): A large 32-bit floating point value used to mark the end of a waveform that may be incomplete due to an overflow.

kyupy.wave_sim.TMIN = np.float32(-1.7014118e+38): A large negative 32-bit floating point value used at the beginning of waveforms that start with logic-1.

class kyupy.wave_sim.WaveSim(circuit, delays, sims=8, c_caps=16, a_ctrl=None, c_reuse=False, strip_forks=False)

A waveform-based combinational logic timing simulator running on CPU.

Parameters:

circuit – The circuit to simulate.
delays – One or more delay annotations for the circuit (see kyupy.sdf.DelayFile.iopaths() for details). Each parallel simulation may use the same delays or different delays, depending on the use-case (see simctl_int).
sims – The number of parallel simulations.
c_caps – The number of floats available in each waveform. Values must be positive and a multiple of 4. Waveforms encode the signal switching history by storing transition times. The waveform capacity roughly corresponds to the number of transitions that can be stored. A capacity of n can store at least n-2 transitions. If more transitions are generated during simulation, the latest glitch is removed (freeing up two transition times) and an overflow flag is set. If an integer is given, all waveforms are set to that same capacity. With an array of length len(circuit.lines) the capacity is set individually for each intermediate waveform.
a_ctrl – An integer array controlling the accumulation of weighted switching activity during simulation. Its shape must be (len(circuit.lines), 3). a_ctrl[...,0] is the index into the accumulation buffer, -1 means ignore. a_ctrl[...,1] is the (integer) weight for a rising transition, a_ctrl[...,2] is the (integer) weight for a falling transition. The accumulation buffer (abuf) is allocated automatically if a_ctrl is given.
c_reuse – If enabled, memory of intermediate signal waveforms will be re-used. This greatly reduces memory footprint, but intermediate signal waveforms may become unaccessible after a propagation.
strip_forks – If enabled, the simulator will not evaluate fork nodes explicitly. This saves simulation time and memory by reducing the number of nodes to simulate, but (interconnect) delay annotations of lines read by fork nodes are ignored.

s

Information about the logic values and transitions around the sequential elements (flip-flops) and ports.

The first 3 values are read by s_to_c(). The remaining values are written by c_to_s().

The elements are as follows:

s[0] (P)PI initial value
s[1] (P)PI transition time
s[2] (P)PI final value
s[3] (P)PO initial value
s[4] (P)PO earliest arrival time (EAT): The time at which the output transitioned from its initial value.
s[5] (P)PO latest stabilization time (LST): The time at which the output settled to its final value.
s[6] (P)PO final value
s[7] (P)PO capture value: probability of capturing a 1 at a given capture time
s[8] (P)PO sampled capture value: decided by random sampling according to a given seed.
s[9] (P)PO sampled capture slack: (capture time - LST) - decided by random sampling according to a given seed.
s[10] Overflow indicator: If non-zero, some signals in the input cone of this output had more transitions than specified in c_caps. Some transitions have been discarded, the final values in the waveforms are still valid.

simctl_int

Integer array for per-simulation delay configuration.

simctl_int[0] delay dataset or random seed for picking a delay. By default, each sim has a unique seed.
simctl_int[1] Method for picking a delay:
- 0: seed parameter of c_prop() directly specifies dataset for all simulations
- 1: simctl_int[0] specifies dataset on a per-simulation basis
- 2 (default): simctl_int[0] and seed parameter of c_prop() together are a random seed for picking a delay dataset.

simctl_float

Float array for per-simulation delay configuration.

simctl_float[0] factor to be multiplied with each delay (default=1.0).

s_to_c()

Transfers values of sequential elements and primary inputs to the combinational portion.

Waveforms are generated on the input lines of the combinational circuit based on the data in s.

c_prop(sims=None, seed=1, delta=0)

Propagates all waveforms from the (pseudo) primary inputs to the (pseudo) primary outputs.

Parameters:

sims – Number of parallel simulations to execute. If None, all available simulations are performed.
seed – Seed for picking delays. See also: simctl_int.

c_to_s(time=np.float32(1.7014118e+38), sd=0.0, seed=1)

Simulates a capture operation at all sequential elements and primary outputs.

Propagated waveforms at the outputs of the combinational circuit at and around the given capture time are analyzed and the results are stored in s.

Parameters:

time – The desired capture time. By default, a capture of the settled value is performed.
sd – A standard deviation for uncertainty in the actual capture time.
seed – The random seed for a capture with uncertainty.

s_ppo_to_ppi(time=0.0)

Re-assigns the last sampled capture of the PPOs to the appropriate pseudo-primary inputs (PPIs). Each PPI transition is constructed from the final value of the previous assignment, the given time, and the sampled captured value of its PPO. Reads and modifies s.

Parameters:: time – The transition time at the inputs (usually 0.0).

class kyupy.wave_sim.WaveSimCuda(circuit, delays, sims=8, c_caps=16, a_ctrl=None, c_reuse=False, strip_forks=False)

A GPU-accelerated waveform-based combinational logic timing simulator.

The API is identical to WaveSim. See there for complete documentation.

All internal memories are mirrored into GPU memory upon construction. Some operations like access to single waveforms can involve large communication overheads.

s_to_c()

Transfers values of sequential elements and primary inputs to the combinational portion.

Waveforms are generated on the input lines of the combinational circuit based on the data in s.

c_prop(sims=None, seed=1, op_from=0, op_to=None, delta=0)

Propagates all waveforms from the (pseudo) primary inputs to the (pseudo) primary outputs.

Parameters:

sims – Number of parallel simulations to execute. If None, all available simulations are performed.
seed – Seed for picking delays. See also: simctl_int.

c_to_s(time=np.float32(1.7014118e+38), sd=0.0, seed=1)

Simulates a capture operation at all sequential elements and primary outputs.

Propagated waveforms at the outputs of the combinational circuit at and around the given capture time are analyzed and the results are stored in s.

Parameters:

time – The desired capture time. By default, a capture of the settled value is performed.
sd – A standard deviation for uncertainty in the actual capture time.
seed – The random seed for a capture with uncertainty.

s_ppo_to_ppi(time=0.0)

Re-assigns the last sampled capture of the PPOs to the appropriate pseudo-primary inputs (PPIs). Each PPI transition is constructed from the final value of the previous assignment, the given time, and the sampled captured value of its PPO. Reads and modifies s.

Parameters:: time – The transition time at the inputs (usually 0.0).

Simulators

Logic Simulation - kyupy.logic_sim

Timing Simulation - kyupy.wave_sim

Logic Simulation - `kyupy.logic_sim`

Timing Simulation - `kyupy.wave_sim`